Semiconductor wafer composed of monocrystalline silicon

ABSTRACT

A semiconductor wafer of single-crystal silicon includes: a polished front side and a back side; a denuded zone, which extends from the polished front side toward the back side to a depth of not less than 45 μm; and a region adjacent to the denuded zone, the region having bulk micro defect (BMD) seeds, which are capable of being developed into BMDs. A density of the BMDs at a distance of 120 μm from the front side is not less than 3×10 9  cm −3 .

CROSS-REFERENCE TO PRIOR APPLICATIONS

This application is a U.S. National Phase Application under 35 U.S.C. §371 of International Application No. PCT/EP2018/077497, filed on Oct. 9,2018, and claims benefit to German Patent Application No. DE 10 2017 219255.0, filed on Oct. 26, 2017. The International Application waspublished in German on May 2, 2019 as WO 2019/081201 under PCT Article21(2).

FIELD

The present invention relates to a semiconductor wafer made ofsingle-crystal silicon having a front side and a back side.

BACKGROUND

A denuded zone is a region of a semiconductor wafer that extends fromthe front side in the direction of the back side over a certain depthand in which oxygen precipitates known as BMDs (bulk micro defects) arenot formed. The denuded zone is typically intended as a location foraccommodating electronic components.

Adjacent to the denuded zone is a region that extends further into theinterior (bulk) of the semiconductor wafer and contains BMD Nuclei. BMDNuclei are developed into BMDs by means of a heat treatment. BMDs act asso-called internal getters, which in particular can bond metallicimpurities. The development of BMD Nuclei into BMDs is also possible inthe course of a heat treatment that is used primarily for constructionof electronic components in the denuded zone.

The presence of vacancies in the single crystal is advantageous whencomparatively high densities of BMDs are sought. US 2002/0170631 A1describes a process for producing a semiconductor wafer ofsingle-crystal silicon with a deep denuded zone. The process includes aheat treatment (RTA treatment, rapid thermal anneal) of thesemiconductor wafer, which includes a short-duration rapid heating andcooling of the semiconductor wafer. The RTA treatment is to be performedin an atmosphere containing oxygen in a concentration of not less than100 ppma and not more than 10,000 ppma. The described process ismoreover conceived so as to form a concentration profile of vacancies inwhich the peak density of vacancies is achieved in the middle betweenthe front side and the back side of the semiconductor wafer or near tothe middle. Since the concentration profiles of the vacancies, of theBMDs seeds and of the BMDs correlate the peak density of BMDs islikewise found in the middle or near to the middle.

The production of modern integrated circuits with 3-D architecturenecessitates the provision of a denuded zone which extends comparativelydeep into the semiconductor wafer and an adjoining region including BMDNuclei which may be developed into BMDs, wherein the distance betweenthe BMDs and the denuded zone should be as small as possible. One knownprocedure includes through silicon via (TSV) fabrication andgrinding-back of the semiconductor wafer from the back side until farbeyond the middle of the semiconductor wafer (M. Motoyoshi, Proceedingsof the IEEE, Vol. 97, No. 1, January 2009). The proximity of the BMDs tothe denuded zone is said to ensure that in the ground-back semiconductorwafer too there is a sufficient density of getter centres, in particulareven during construction of structures of electronic components.

SUMMARY

An embodiment of the present invention provides a semiconductor wafer ofsingle-crystal silicon that includes: a polished front side and a backside; a denuded zone, which extends from the polished front side towardthe back side to a depth of not less than 45 μm; and a region adjacentto the denuded zone, the region comprising bulk micro defect (BMD)seeds, which are capable of being developed into BMDs. A density of theBMDs at a distance of 120 μm from the front side is not less than 3×109cm-3.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be described in even greater detail belowbased on the exemplary figures. The invention is not limited to theexemplary embodiments. Other features and advantages of variousembodiments of the present invention will become apparent by reading thefollowing detailed description with reference to the attached drawingswhich illustrate the following:

FIG. 1 and FIG. 2 respectively show the radial profile of the averagedensity of BMDs using example representatives of semiconductor wafers.

FIG. 3 and FIG. 4 respectively show the radial profile of the distanceusing example representatives of semiconductor wafers.

FIG. 5 and FIG. 6 respectively show the average size of the BMDs as afunction of their radial position using example representatives ofsemiconductor wafers.

FIG. 7 to FIG. 12 respectively show a depth profile of the density ofBMDs using the example representatives of semiconductor wafers.

FIG. 13 and FIG. 14 show analysis results obtained after analysis of theback sides of representatives semiconductor wafers.

FIG. 15 shows this difference with reference to a box whisker plot.

DETAILED DESCRIPTION

The present invention provides a semiconductor wafer of single-crystalsilicon that better fulfils the recited requirements.

An embodiment of the present invention provides a semiconductor wafer ofsingle-crystal silicon, including: a polished front side and a backside; a denuded zone, that extends from the polished front side towardthe back side to a depth of not less than 30 μm; and a region adjacentto the denuded zone and including BMD Nuclei, which may be developedinto BMDs. A density of the BMDs at a distance of 120 μm from the frontside is not less than 2×10⁸ cm⁻³.

The semiconductor wafer of single crystalline silicon is either anuncoated semiconductor wafer or a semiconductor wafer coated with atleast one epitaxial layer. When the semiconductor wafer ofsingle-crystal silicon is coated with an epitaxial layer, the uppersurface of the epitaxial layer forms the front side of the semiconductorwafer. The at least one epitaxial layer preferably has a thickness ofnot less than 1 μm and not more than 5 μm.

An embodiment of the present invention provides a semiconductor wafermade of single-crystal silicon having a front side and a back side. Thesemiconductor wafer has a denuded zone, which extends from the frontside in the direction of the back side to a certain depth and a regionwhich is adjacent to the denuded zone and contains BMD Nuclei.

In a first preferred embodiment of the invention, the semiconductorwafer of single-crystal silicon is an uncoated substrate wafer ofsingle-crystal silicon whose denuded zone extends from the polishedfront side to a depth of not less than 45 μm. The semiconductor wafer inthe region adjacent to the denuded zone includes BMD Nuclei after whosedevelopment into BMDs, the density of the BMDs at a distance of 120 μmfrom the front side is not less than 3×10⁹ cm⁻³.

In a second preferred embodiment of the invention, the semiconductorwafer of single-crystal silicon is a substrate wafer of single-crystalthat is coated with at least one epitaxial layer of single-crystalsilicon and has a denuded zone that extends from the polished front sideof the coated substrate wafer to a depth of not less than 45 μm. Thesemiconductor wafer in the region adjacent to the denuded zone includesBMD Nuclei after whose development into BMDs, the density of the BMDs ata distance of 120 μm from the front side is not less than 3×10⁹ cm⁻³.

The at least one epitaxial layer has a thickness of preferably not lessthan 1 μm and not more than 5 μm. The semiconductor wafer of the secondpreferred embodiment of the invention is preferably an epitaxial coatedsubstrate wafer with n/n⁻ doping or p/p⁻ doping. The dopant of then-type is preferably phosphorous and the dopant of the p-type ispreferably boron.

In a third preferred embodiment of the invention, the semiconductorwafer of single-crystal silicon is an uncoated substrate wafer ofsingle-crystal silicon, which has a denuded zone that extends from thepolished front side to a depth of not less than 30 μm. The semiconductorwafer in the region adjacent to the denuded zone includes BMD Nucleiafter whose development into BMDs, the density of the BMDs at a distanceof 120 μm from the front side is not less than 2×10⁸ cm⁻³. Producing asemiconductor wafer of the third embodiment of the invention requires acomparatively small number of process steps.

An inventive semiconductor wafer of single-crystal silicon includes, ina region below the denuded zone, BMD Nuclei, which may be developed intoBMDs. It is preferable that the density of developed BMDs decreases froma peak density in the direction of the central plane. The semiconductorwafer of single-crystal silicon may be ground back to a residualthickness from the back side, while preferably retaining the region inwhich the peak density of BMDs may be developed.

In the denuded zone, the lifetime of minority charge carriers ispreferably greater than 1000 μs on average.

The back side of an embodiment of a semiconductor wafer ofsingle-crystal silicon is preferably burdened with not more than 100defects.

The production of a semiconductor wafer of the first preferredembodiment of the invention includes the following process steps:

-   -   providing a substrate wafer of single-crystal silicon;    -   polishing the substrate wafer by DSP;    -   loading an RTA reactor with the substrate wafer;    -   a first RTA treatment of the substrate wafer at a temperature in        a temperature range of not less than 1275° C. and not more than        1295° C. for a period of not less than 15 s and not more than 30        s in an atmosphere consisting of argon and oxygen having a        proportion of oxygen of not less than 0.5 vol % and not more        than 2 vol %;    -   cooling the substrate wafer after the first RTA treatment to a        temperature of not more than 800° C., wherein a gas feed to the        semiconductor wafer is reset to 100 vol % argon;    -   a second RTA treatment of the substrate wafer at a temperature        in a temperature range of not less than 1280° C. and not more        than 1300° C. for a period of not less than 20 s and not more        than 35 s in an atmosphere consisting of argon;    -   removing an oxide layer from a front side of the semiconductor        wafer; and    -   polishing the front side of the substrate wafer by CMP.

DSP (double side polishing) is a polishing procedure in the course ofwhich the front side and the back side of a substrate wafer are polishedsimultaneously.

CMP (chemical mechanical polishing) is a polishing procedure in thecourse of which the front side or the back side of a substrate wafer ispolished.

The oxide layer present on the substrate wafer after the first RTAtreatment is removed from the front side of the substrate wafer,preferably by treating the substrate wafer with aqueous HF solution. Theaqueous HF solution preferably contains not less than 0.5% by weight ofHF and not more than 2% by weight of HF and the duration of thetreatment is preferably not less than 150 s and not more than 350 s.

The production of a semiconductor wafer of the second preferredembodiment of the invention includes the following process steps:

-   -   providing a substrate wafer of single-crystal silicon;    -   polishing the substrate wafer by DSP;    -   polishing the front side of the substrate wafer by CMP;    -   depositing at least one epitaxial layer of single-crystal        silicon on the front side of the substrate wafer;    -   loading an RTA reactor with the coated substrate wafer;    -   a first RTA treatment of the coated substrate wafer at a        temperature in a temperature range of not less than 1275° C. and        not more than 1295° C. for a period of not less than 15 s and        not more than 30 s in an atmosphere consisting of argon and        oxygen having a proportion of oxygen of not less than 0.5 vol %        and not more than 2 vol %;    -   cooling of the coated substrate wafer after the first RTA        treatment to a temperature of not more than 800° C., wherein a        gas feed to the semiconductor wafer is reset to 100 vol % argon;    -   a second RTA treatment of the coated substrate wafer at a        temperature in a temperature range of not less than 1280° C. and        not more than 1300° C. for a period of not less than 20 s and        not more than 35 s in an atmosphere consisting of argon;        removing an oxide layer from a front side of the coated        substrate wafer; and    -   polishing the front side of the coated substrate wafer by CMP.

The oxide layer present on the coated substrate wafer after the firstRTA treatment is removed from the front side of the coated substratewafer, preferably by treating the coated substrate wafer with aqueous HFsolution. The aqueous HF solution preferably contains not less than 0.5%by weight of HF and not more than 2% by weight of HF and the duration ofthe treatment is preferably not less than 150 s and not more than 350 s.

The deposition of the at least one epitaxial layer on the substratewafer is preferably carried out by CVD (chemical vapour deposition) andpreferably in a single wafer reactor, for example such as is describedin US 2010/0213168 A1. A preferred deposition gas containstrichlorosilane as the silicon source. The deposition temperature isthen preferably not less than 1110° C. and not more than 1180° C.,particularly preferably 1130° C. Furthermore, the deposition gaspreferably contains a dopant of the n-type or of the p-type.

The production of a semiconductor wafer of the third preferredembodiment of the invention includes the following process steps:

-   -   providing a substrate wafer of single-crystal silicon;    -   loading an RTA reactor with the substrate wafer;    -   a first RTA treatment of the substrate wafer at a temperature in        a temperature range of not less than 1250° C. and not more than        1310° C. for a period of not less than 5 s and not more than 40        s in an atmosphere consisting of nitrogen and oxygen having a        proportion of oxygen of not less than 0.5 vol % and not more        than 3.0 vol %;    -   cooling the substrate wafer after the first RTA treatment to a        temperature of not more than 800° C., wherein a gas feed to the        substrate wafer is reset to 100 vol % argon;    -   a second RTA treatment of the substrate wafer at a temperature        in a temperature range of not less than 1280° C. and not more        than 1300° C. for a period of not less than 20 s and not more        than 35 s in an atmosphere consisting of argon;    -   polishing the substrate wafer by DSP; and    -   polishing the front side of the substrate wafer by CMP.

The oxide layer present on the substrate wafer after the first RTAtreatment is removed from the front side of the substrate wafer bypolishing the substrate wafer by DSP. The thus achieved material removalfrom the front side and the back side of the substrate wafer ispreferably not less than 8 μm in each case.

The step of providing a substrate wafer of a single crystalline siliconis a step recited at the beginning of the production processesdescribed. The substrate wafer is preferably cut from a single crystalof single-crystal silicon pulled by the CZ method and subjected tofurther processing. In the CZ method silicon is melted in a cruciblemade of quartz and the single-crystal grows at the end of a seed crystalwhich is immersed in the resulting melt and raised. The cruciblematerial is partially dissolved by contact with the melt and in this wayprovides oxygen later required for developing BMDs.

The single crystal of single-crystal silicon preferably has a diameterof not less than 300 mm. The substrate wafer cut from the single crystalpreferably originates from n region. N region describes single crystalsilicon which contains neither agglomerates of vacancies noragglomerates of silicon interstitial atoms nor OSF defects (oxidationinduced stacking faults). Such material is formed for example when thesingle-crystal is pulled according to the CZ method and the V/G ratio ofpulling speed V and axial temperature gradient G at the crystallizationboundary is controlled such that it remains between critical limits.

The single-crystal from which the provided substrate wafer ofsingle-crystal silicon is cut is preferably not intentionally doped withnitrogen or carbon. Accordingly the provided substrate wafer ofsingle-crystal silicon contains nitrogen in a concentration ofpreferably not more than 3×10¹² atoms/cm³ and carbon in a concentrationof preferably not more than 2.5×10¹⁵ atoms/cm³. The concentration ofoxygen in the provided substrate wafer is preferably not less than4.5×10¹⁷ atoms/cm³ and not more than 5.5×10¹⁷ atoms/cm³, taking accountof the calibration factor as per new ASTM.

The substrate wafer cut from the single-crystal may be subjected tofurther processing using mechanical and chemical processing steps suchas grinding and etching. It is preferable to provide a substrate waferof single-crystal silicon that has been subjected to at least onematerial-removing processing operation. The last material-removingtreatment carried out before providing the substrate wafer is preferablya treatment by etching.

The provided and optionally epitaxial coated substrate layer ofsingle-crystal silicon is loaded into an RTA reactor and in the courseof the first RTA treatment, preferably heated to the target temperatureat a rate of not less than 50° C./s.

Following the first RTA treatment, the provided and optionally epitaxialcoated substrate layer remains in the RTA reactor and is cooled,preferably to a temperature of not more than 800° C. The cooling rate ispreferably not less than 30° C./s. The gas feed into the RTA reactor issimultaneously switched to 100% argon.

The provided and optionally epitaxial coated substrate layer ofsingle-crystal silicon is, in the course of the second RTA treatment,preferably heated to the target temperature at a rate of not less than50° C./s.

The period between the end of the first RTA treatment and the beginningof the second RTA treatment is preferably not less than 25 s and notmore than 50 s.

Burdening of a semiconductor wafer according to the invention (accordingto the first, second and third embodiment) with defects is preferablycurtailed by passing oxygen (100 vol %) through the RTA reactor prior tothe first RTA treatment, preferably with a flowrate of not less than 8slm and not more than 18 slm (standard litres per minute). The defectburden of the semiconductor wafer may be analysed using ahigh-resolution laser scattering system for example. Analysis resultscontained herein were obtained in part using an edge and back sideinspection module (EBI) from Rudolph Technologies which allows fordetermination of defects such as particles, scratches, surface defectsand haze on the back side and in part with a KLA Tencor Surfscan SP3inspection system which detects LLS defects (localized light scatterers)on the front side.

An embodiment of the present invention provides a semiconductor wafer ofsingle-crystal silicon, which includes a region having BMD Nuclei, whichis located below the denuded zone and is adjacent to the denuded zone.BMD Nuclei are centres including vacancies where BMDs may develop aftera precipitation heat treatment. The precipitation heat treatment is nota constituent of a process for producing a semiconductor wafer accordingto the invention but is used to test whether BMDs can be developed inthe required density or to develop BMDs that exhibit their activity asgetter centres. The precipitation heat treatment is accordinglyperformed either as a test or preferably in the course of a furtherprocessing of the semiconductor wafer of single-crystal silicon intoelectronic components.

A typical precipitation heat treatment for test purposes consists of atwo-stage precipitation heat treatment of the semiconductor waferaccording to the invention under oxygen at a temperature of 780° C. fora duration of 3 h (stage 1, stabilization step) and at a temperature of1000° C. for a duration of 16 h (stage 2, growth step).

The density of the developed BMDs may be determined along a broken edgeof the semiconductor wafer for example by IR laser scattering tomographyas the analytical method using an MO-441 detector from RaytexCorporation, Japan. Evaluation of the measured results is typicallyperformed by plotting in a diagram the average density of BMDs (D_(BMD))along the radius of the semiconductor wafer (averaged over a depth of7-300 μm at each radial position of measurement, wherein the BMD defectdensity is measured every 5 μm in the depth axis) for example at least25 radial positions of measurement P which are equidistant from oneanother. Also determined at the radial positions of measurement P is thedistance DZ1 from the first encountered BMD to the front side, thisdistance being plotted in a diagram along the radius of thesemiconductor wafer. The arithmetic average of the distances DZ1represents the depth to which the denuded zone extends from the polishedfront side into the interior of the semiconductor wafer. Also plottablein a diagram is the average size s_(av) of BMDs (measured over a depthof 7-300 μm at each radial position of measurement, the BMD defect sizebeing measured in the depth axis every 5 μm) as a function of the radialposition of measurement P and also the profile of the density of BMDs(D_(BMD)) in the depth direction, i.e. along the distance d to the frontside of the semiconductor wafer, based on a particular radial positionof measurement P.

The invention is further elucidated herein below with the aid ofexamples and with reference to drawings.

Substrate wafers of single-crystal silicon having a diameter of 300 mmwere provided. The substrate wafers consisted of n region and hadsurfaces in an etched state. A first portion of the substrate wafers wassubjected to the process according to the invention for producingsemiconductor wafers according to the first preferred embodiment.

Prior to the first RTA treatment, oxygen (100 vol %) was passed throughthe RTA reactor at a flowrate of 10 slm. The first RTA treatment wasthen undertaken at a temperature of 1290° C. in an atmosphere of argonand oxygen (oxygen proportion 1 vol %). The duration of the first RTAtreatment at this temperature was 20 s. The substrate wafers weresubsequently cooled to a temperature of 600° C. and held at thistemperature over a period of 40 s while the gas feed to thesemiconductor wafers was switched to 100% argon. This was followed bythe second RTA treatment at a temperature of 1295° C. and in an argonatmosphere over a period of 30 s.

The oxide layer formed was then removed from the substrate wafers andthe front sides of the substrate wafers polished by CMP. The resultingsemiconductor wafers according to the first embodiment of the inventionwere subjected to the two-stage precipitation heat treatment providedfor test purposes.

A second portion of the substrate wafers was subjected to the processaccording to the invention for producing semiconductor wafers accordingto the third preferred embodiment.

Prior to the first RTA treatment, oxygen (100 vol %) was passed throughthe RTA reactor at a flowrate of 10 slm. The first RTA treatment wasthen undertaken at a temperature of 1290° C. in an atmosphere composedof nitrogen and oxygen (oxygen proportion 1 vol %). The duration of thefirst RTA treatment at this temperature was 20 s. The substrate waferswere subsequently cooled to a temperature of 600° C. and held at thistemperature over a period of 40 s while the gas feed to thesemiconductor wafers was switched to 100% argon.

This was followed by the second RTA treatment at a temperature of 1295°C. and in an argon atmosphere over a period of 30 s.

The substrate wafers were subsequently polished initially by DSP andthen by CMP and the resulting semiconductor wafers according to thethird embodiment of the invention were likewise subjected to thetwo-stage precipitation heat treatment provided for test purposes.

FIG. 1 and FIG. 2 respectively show the radial profile of the averagedensity D_(BMD) of BMDs using the example of representatives ofsemiconductor wafers of the first embodiment (FIG. 1) and of the thirdembodiment (FIG. 2).

FIG. 3 and FIG. 4 respectively show the radial profile of the distanceDZ1 using the example of representatives of semiconductor wafers of thefirst embodiment (FIG. 3) and of the third embodiment (FIG. 4) with acorresponding depth of the denuded zone of not less than 45 μm (FIG. 3)and of not less than 30 μm (FIG. 4).

FIG. 5 and FIG. 6 respectively show the average size s_(av) of the BMDsas a function of their radial position using the example ofrepresentatives of semiconductor wafers of the first embodiment (FIG. 5)and of the third embodiment (FIG. 6).

FIG. 7 to FIG. 12 respectively show a depth profile of the densityD_(BMD) of BMDs using the example of representatives of semiconductorwafers of the first embodiment (FIG. 7, FIG. 8 and FIG. 9) and of thethird embodiment (FIG. 10, FIG. 11 and FIG. 12), wherein the depthprofile in the centre (P=0 mm; FIG. 7 and FIG. 10), at half radius (P=75mm; FIG. 8 and FIG. 11) and at the radial distance P=140 mm (FIG. 9 andFIG. 12) was determined.

FIG. 13 and FIG. 14 show analysis results obtained after analysis of theback sides of representatives of the semiconductor wafers with theabovementioned edge and back side inspection module (EBI). FIG. 13 showsa typical defect burden of the back side of an inventive semiconductorwafer of 8 defects greater than 0.2 μm and less than 100 defects,wherein during production of the semiconductor wafer care was taken toensure that pure oxygen was passed through the RTA reactor at a flowrateof 10 slm prior to the first RTA treatment. If the passing of oxygenthrough the reactor is dispensed with the defect burden of the back sideis markedly greater and annular defect regions having high defectdensities are detectable (FIG. 14) (all defects larger than 0.2 μm werein turn measured and depicted). On the other hand it is not advantageousto set the flowrate of the oxygen to values of for example 25 slm priorto the first RTA treatment. In this case the number of LLS defectshaving a latex sphere equivalent of >0.13 μm is unacceptably high. Thisis not the case when the flow rate of the oxygen is selected to fallwithin the range of not less than 8 slm and not more than 18 slm. FIG.15 shows this difference with reference to a box whisker plot, whereinthe number N of LLS defects has been normalized. It is generallyadvantageous to recondition the oxidation state of the RTA reactor atregular intervals by running in the presence of wafer dummies. This ispreferably carried out in an ambient of Ar/O₂ having an 02 vol %proportion of 75-100% and a flow of 20-25 slm.

While embodiments of the invention have been illustrated and describedin detail in the drawings and foregoing description, such illustrationand description are to be considered illustrative or exemplary and notrestrictive. It will be understood that changes and modifications may bemade by those of ordinary skill within the scope of the followingclaims. In particular, the present invention covers further embodimentswith any combination of features from different embodiments describedabove and below. Additionally, statements made herein characterizing theinvention refer to an embodiment of the invention and not necessarilyall embodiments.

The terms used in the claims should be construed to have the broadestreasonable interpretation consistent with the foregoing description. Forexample, the use of the article “a” or “the” in introducing an elementshould not be interpreted as being exclusive of a plurality of elements.Likewise, the recitation of “or” should be interpreted as beinginclusive, such that the recitation of “A or B” is not exclusive of “Aand B,” unless it is clear from the context or the foregoing descriptionthat only one of A and B is intended. Further, the recitation of “atleast one of A, B and C” should be interpreted as one or more of a groupof elements consisting of A, B and C, and should not be interpreted asrequiring at least one of each of the listed elements A, B and C,regardless of whether A, B and C are related as categories or otherwise.Moreover, the recitation of “A, B and/or C” or “at least one of A, B orC” should be interpreted as including any singular entity from thelisted elements, e.g., A, any subset from the listed elements, e.g., Aand B, or the entire list of elements A, B and C.

1-4. (canceled) 5: A semiconductor wafer of single-crystal silicon, thesemiconductor wafer comprising: a polished front side and a back side; adenuded zone, which extends from the polished front side toward the backside to a depth of not less than 45 μm; and a region adjacent to thedenuded zone, the region comprising bulk micro defect (BMD) seeds, whichare capable of being developed into BMDs, wherein a density of the BMDsat a distance of 120 μm from the front side is not less than 3×10⁹ cm⁻³.6: The semiconductor wafer according to claim 5 comprising an epitaxiallayer of single-crystal silicon, wherein an upper surface of theepitaxial layer forms the front side of the semiconductor wafer, thusincreasing the depth to which the denuded zone extends by the magnitudeof the thickness of the epitaxial layer. 7: The semiconductor waferaccording to claim 5, wherein the back side of the semiconductor waferis burdened with not more than 100 defects greater than 0.2 μm.